A field-effect transistor (FET) is a kind of semiconductor devices that controls the electric current between a source electrode and a drain electrode by applying a voltage to a gate electrode to provide a gate for the flow of electrons or holes depending on an electric field of a channel.
FETs are used as switching elements and amplifying elements due to their properties. Since an FET shows a small gate current and has a flat profile, it can be easily manufactured or integrated compared to a bipolar transistor. Therefore, an FET is now an indispensable element in an integrated circuit used in electronic devices.
There are electronic devices including FETs, of which basic structure is MIS (Metal Insulator Semiconductor) structure. Examples of the devices are a switching element, a memory, a logic circuit; other examples are an LSI (Large Scale Integrated Circuit) and an AM-TFT (Active Matrix Thin Film Transistor), which are formed by integrating the aforementioned elements. In the FETs, silicon oxide, oxynitride, and nitride have been used as gate insulating films and capacitor insulating films for a long time. The insulating films of these silicon compounds are not only excellent as insulating films, but also have high affinity with the MIS process.
However, in recent years and continuing, there is demand for electronic devices that are more highly integrated and that consume less power. Therefore, there has been proposed a technology for using, as the insulating film, a so-called high-k insulating film that has significantly a higher relative permittivity than SiO2.
For example, in a microscopic MOS (Metal Oxide Semiconductor) device having a gate length of less than or equal to 0.1 μm, when the gate insulating layer of FET is made of SiO2, the film thickness needs to be less than or equal to 2 nm, based on the scaling law. However, in this case, the gate leakage current caused by a tunnel current becomes a large problem. One approach to reduce the gate leakage current is increasing the thickness of the gate insulating layer by using the high-k insulating film as the gate insulating layer.
A volatile or non-volatile semiconductor memory is an example of a semiconductor device using the field-effect transistor.
In a volatile memory, the drain electrode of the field-effect transistor and the capacitor are serially connected. By using a high-k insulating film, power consumption can be reduced and high integration is possible. Currently, dielectric layers of capacitors are mainly made of laminated layers of SiO2/SiNx/SiO2. Thus, there is further demand for insulating films having higher relative permittivity.
The writing/erasing voltage can be reduced in a non-volatile semiconductor memory, including a first gate insulating layer that is an insulating film provided between a semiconductor layer and a floating gate electrode, and a second gate insulating layer that is an insulating film provided between a floating gate electrode and a control gate electrode. Specifically, the writing/erasing voltage can be reduced as a result of increasing the coupling ratio by using a high-k insulating film as the second gate insulating film of the non-volatile semiconductor memory. Currently, second gate insulating layers are mainly made of laminated layers of SiO2/SiNx/SiO2. Thus, there is further demand for insulating films having a higher relative permittivity.
In an AM-TFT used in displays, if a high-k insulating film is used in the gate insulating film, high saturation currents can be attained and the ON/OFF operation can be controlled by a low gate voltage, so that the power consumption can be reduced.
Typically, as materials of a high-k insulating film, metal oxide of metals such as Hf, Zr, Al, Y, and Ta have been discussed. Specific examples are HfO2, ZrO2, Al2O3, Y2O3, Ta2O5; silicates of these elements (HfSiO, ZrSiO); aluminates of these elements (HfAlO, ZrAlO), and nitrides of these elements (HfON, ZrON, HfSiON, ZrSiON, HfAlON, ZrAlON).
Meanwhile, in regard to ferroelectric memory materials, a perovskite structure and related substances have been discussed. The perovskite structure is expressed by ABO3, which is typically a combination of a divalent metal ion (A site) and a tetravalent metal ion (B site), or a combination of trivalent metal ions corresponding to both the A site and the B site. Examples are SrTiO3, BaZrO3, CaSnO3, and LaAlO3. Furthermore, there are many crystals in which the B site is occupied by two kinds of ions, such as SrBi0.5Ta0.5O3 and BaSc0.5Nb0.5O3.
Furthermore, there is a series of crystals referred to as a layer type perovskite structure. This is expressed by (AO)m(BO2)n, in which an m number of AO layers and an n number of BO2 layers are laminated. For example, there are Sr2TiO4, Sr3Ti2O7, and Sr4Ti3O10, with respect to a basic structure of SrTiO3 (m=n=1). According to such crystal structures, the composition ratio of A ions and B ions may be varied. Accordingly, a wide variety of crystal groups may appear, including the combination of B site ions. In the present application, a “perovskite structure related crystal” means a crystal having a perovskite structure or a layer type perovskite structure.
Incidentally, when a polycrystalline material is used as a gate insulating layer, a large leakage current flows at the interfaces of the crystal grain boundaries. Therefore, the function of the gate insulating film is degraded. Furthermore, when the crystal system has anisotropy, properties of the transistor may become irregular due to dielectric constant anisotropy.
Patent documents 1 and 2 disclose methods of decreasing leakage currents in the gate insulating layer, by using an amorphous insulating film made of a high-dielectric-constant silicate as the gate insulating layer.
Patent document 3 discloses a method of decreasing leakage currents in the gate insulating layer, by using an amorphous insulating film primarily made of A2B2O7 having a pyrochlore structure, as the gate insulating layer.
Patent documents 4, 5, and 6 disclose methods of decreasing leakage currents in the gate insulating layer, by using laminated films including a high dielectric constant film as the gate insulating layer. Patent document 7 discloses a method of decreasing leakage currents in the gate insulating layer, by forming a high dielectric constant film of epitaxial growth on a substrate, and performing a heating process so that elements in the substrate and metal oxide elements in the gate insulating film are mixed together.
Furthermore, patent document 8 discloses a TFT device in which laminated films, including an inorganic oxide film having a high dielectric constant and an organic polymer film, are used as the gate insulating layer.
However, the problem with the insulating film disclosed in patent documents 1 and 2 is that the relative permittivity cannot be sufficiently increased, because the insulating film has plenty of SiO2 content.
With the material disclosed in patent document 3, the gate insulating layer includes a crystalline phase. Therefore, an amorphous phase is formed in the region of an extremely narrow process condition. Accordingly, there are problems in the manufacturing process.
The problem with the methods disclosed in patent documents 4 through 8 is that the manufacturing process is complex and manufacturing costs are high.
Accordingly, there is a need for a field-effect transistor, a semiconductor memory, a display element, an image display device, and a system, including an insulating film having a high relative permittivity and a small amount of leakage currents formed by a simple method and at low cost.    Patent Document 1: Japanese Laid-Open Patent Application No. H11-135774    Patent Document 2: Japanese Patent No. 3637325    Patent Document 3: Japanese Laid-Open Patent Application No. 2002-270828    Patent Document 4: Japanese Laid-Open Patent Application No. 2002-134737    Patent Document 5: Japanese Patent No. 3773448    Patent Document 6: Japanese Laid-Open Patent Application No. 2003-258243    Patent Document 7: Japanese Patent No. 3831764    Patent Document 8: Japanese Laid-Open Patent Application No. 2008-16807    Patent Document 9: Japanese Laid-Open Patent Application No. 2001-319927    Patent Document 10: Japanese Laid-Open Patent Application No. 2002-367980    Patent Document 11: Japanese Laid-Open Patent Application No. 2004-241751    Patent Document 12: Japanese Laid-Open Patent Application No. 2007-165724    Patent Document 13: Japanese Laid-Open Patent Application No. 2008-91904